TX CH0 config0 register
| OUT_AUTO_WRBACK_CH0 | Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. |
| OUT_EOF_MODE_CH0 | EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA |
| OUTDSCR_BURST_EN_CH0 | Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. |
| OUT_ECC_AES_EN_CH0 | When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. |
| OUT_CHECK_OWNER_CH0 | Set this bit to enable checking the owner attribute of the link descriptor. |
| OUT_MEM_BURST_LENGTH_CH0 | Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes |
| OUT_PAGE_BOUND_EN_CH0 | Set this bit to 1 to make sure AXI read data don’t cross the address boundary which define by mem_burst_length |
| OUT_REORDER_EN_CH0 | Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection |
| OUT_RST_CH0 | Write 1 then write 0 to this bit to reset TX channel |
| OUT_CMD_DISABLE_CH0 | Write 1 before reset and write 0 after reset |
| OUT_ARB_WEIGHT_OPT_DIS_CH0 | Set this bit to 1 to disable arbiter optimum weight function. |